Synopsys offers several Universal DDR controllers, which use a DFI-compliant interface between the Memory or Protocol Controller IP and PHY. The DesignWare Universal DDR
controller family consists of three highperformance products: the Enhanced Universal DDR Memory Controller (uMCTL2), the Universal DDR Protocol Controller (uPCTL), and the Universal DDR Memory Controller (uMCTL), all of which support the JEDEC DDR2, DDR3, LPDDR, LPDDR2, and LPDDR3 SDRAM standards. The uMCTL2 also supports the DDR4 and LPDDR4 SDRAM standards.
The Enhanced Universal DDR Memory Controller (uMCTL2) delivers maximum bandwidth with minimum latency and provides designers with transparent access and complete control of the memory subsystem. This advanced multi-port memory controller accepts memory access requests from up to 16 application-side host ports. Applicationside interfaces can be connected to the uMCTL2 either through standard AMBA AXI/AHB/ACE-lite bus interfaces for one or multiple ports, or via Synopsys’ custom-defined host-interface H-IF for very low latency single-port configurations.
The uMCTL2 Memory Controller supports DDR4 in addition to the standards listed above. The Universal DDR Protocol Controller (uPCTL) serves the memory control needs of applications with simple transactions that do not require an internal scheduler, and can be integrated with custom designed scheduling units. The Universal DDR Memory Controllers (uMCTL and uMCTL2) accept memory access requests from up to 32 application-sidehost ports. Application-side interfaces can be connected to the uMCTL Memory Controller either through the standard AMBA AXI/AHB bus interfaces or via Synopsys custom-defined Extended Native Interface (ENIF).
- Protocol controller (uPCTL) optimized for low latency, high bandwidth, low area and low power (allows integration with a custom scheduler/arbiter)
- Multi-ported memory controller option
- Universal DDR Protocol and Memory Controllers offer a DFI interface and user configurable support for DDR2, DDR3, LPDDR and LPDDDR2/3 SDRAM standards
- uMCTL2 DDR controller architecture with added support for DDR4 and LPDDR4 delivers high performance, low
- Executable .run installation file
- Databook (PDF)
- Release notes (PDF)
- coreConsultant/coreAssembler tools to generate RTL