LPDDR4 IP with patented dynamic self-calibration and adaptive-bit technology, can automatically compensate chip/package/board/memory PVT variation and bit-bit skew.
Dynamic technology delivers the highest DDR performance with the smallest area and the shortest bring-up time.
Both PHY and Controller IP are available, with the option of using a third-party DDR controller through the AHB/APB register interface and DFI3.1 interface.
Excellent techincail support will be provided to ensure success with integration and validation.
- Date rate of 4266Mbps
- Comprehensive LPDDR4 training
- CA training
- DQ read training
- DQ write training
- Write leveling
- Vref training
- PHY is DFI 4.0 compatible and backwards-compatible to earlier DFI standards for simplified integration with existing DFI-compliant Controllers
- PHY includes DSCL technology
- Automatically compensates for DDR interface timing due to static (process-related) variations and dynamic variations due to operating temperature, voltage, and data patterns
- PHY includes DABC technology
- Automatically compensates for bit-bit skew within each byte lane
- Flexible, rectilinear PHY layout offers industry’s smallest PHY area and is hardened to match IO pad frame
- DSCL delivers lowest PHY latency of 0.5 – 1 clock cycles
- PHY (and optionally IO) configured as drop-in hard macro for easy implementation
- Fast and simple system bring-up via DSCL hardware routine
- Maximum data-rate on low-power processes
- Compensate for Board electrical characteristics
- Save 20-30% in area over competing implementations
- Fast and easy memory system bring-up
- Patented DSCL and DABC technology ensures long-term system reliability
- Technical reference manual
- Encrypted Verilog simulation model (ncverilog/vcs)
- .db, .lib, .vg, .lef, .gdsII, .spef, .sdf
- Timing report
- Portable Devices
Block Diagram of the LPDDR4 CNTLR, PHY & IO - ICF 14FF