Northwest Logic’s Low Power Double Data Rate 4 (LPDDR4) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.
The core accepts commands using a simple local interface and translates them to the command sequences required by LPDDR4 SDRAM devices. The core also performs all initialization, refresh and power-down functions.
The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays.
The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.
The core is provided with run-time programmable inputs for all memory timing parameters and configuration settings. This ensures compatibility with all LPDDR4 SDRAM configurations. Add-On Cores such as a Multi-Port Front-End and Reorder Core can be optionally delivered with the core. The core is delivered fully integrated and verified with the target DDR PHY. Northwest Logic supports a broad range of third party and its own soft DDR PHY. Contact Northwest Logic for more information.
- Maximizes bus efficiency via Look- Ahead command processing, Bank Management and Auto-Precharge
- Minimal latency achieved via parameterized pipelining
- Achieves high clock rates with minimal routing constraints
- Supports full rate, half-rate and quarter-rate clock operation
- Multi-mode controller support
- Full run-time configurable timing parameters and memory settings
- Supports LPDDR4 Data Bus Inversion (DBI) and Data Mask (DM)
- Supports self-refresh, partial array self-refresh, power-down, and deep power down modes
- DFI Compatible
- Full set of Add-On Cores available
- Delivered fully integrated and verified with target DDR PHY
- Minimal ASIC gate count
- Broad range of ASIC platforms supported
- Source code available
- Customization and Integration services available
- Core (Netlist or Source Code)
- Testbench (Source Code)
- Complete Documentation
- Expert Technical Support & Maintenance Updates
Block Diagram of the LPDDR4 SDRAM Controller IP Core