The M8051EW+ is the Mentor Graphics M8051W/EW high-performance version of the popular 8051 8-bit microcontroller. The M8051EW+ requires just 2 clocks per machine cycle instead of the 12 clocks per machine cycle required by industry standard 8051 devices. This allows the M8051EW+ to execute instructions six times faster than standard 8051 devices running at the same clock rate. Or, the M8051EW+ can run at one sixth the clock rate of a standard 8051 device and achieve equivalent performance at a fraction of the power consumption.
The ‘On-Chip Instrumentation’ (OCI) debug unit supplied with the Mentor Graphics M8051EW is available as a hardware configuration option with the M8051EW+. When used with the FS2 System Navigator for Mentor Graphics M8051EW Cores, the OCI debug unit supports advanced debug operations (start/stop/ single-step, breakpoints, and trace) through an IEEE 1149.1 (JTAG) interface. Because inclusion of the OCI debug unit is an M8051EW+ configuration option, you can include the OCI debug unit for prototyping and software development and exclude it from your production chips.
The M8051EW+ is a microcode-free design that is software compatible with industry standard 8051 devices, supporting both standard 8051 features and additional features corresponding to Intel 8051, 8031, 80C51BH, 80C31BH, and 87C51 devices and equivalent 8052 devices. The M8051EW+ is supported by several 3rd-party assemblers and C compilers including the 8051 Development Tools from Keil Software.
The M8051EW+ supports up to 1 MB of Program Memory and 1 MB of External Data Memory and can be configured to work with either synchronous or asynchronous memories, using either separate Program and External Data Memory interfaces or a single multiplexed memory interface. Support for slow memories is available through wait states.
- 2 clocks per machine cycle
- Optional OCI debug unit
- Software compatible with Intel 8051, 8031, 87C51, and 8052 equivalents
- Up to 1 MB of External Data Memory
- Up to 1 MB of Program Memory
- Up to 256 bytes of Internal Data Memory
- Support for synchronous or asynchronous memories
- Wait state support for slow Program and External Data Memories
- M8051EW+-specific instruction (MOVC @(DPTR++), A) available for downloading program code to RAM
- Intel-compatible I/O Ports (optional)
- 2 or 3 16-bit timer/counters (optional)
- Full-duplex serial port (optional)
- 25-source, 2 or 4-level interrupt controller with choice of interrupt handling schemes
- 1, 2, 4, or 8 data pointers
- Support for up to 118 user-defined external special function registers (ESFRs), 11 of which may be bit-addressable
- Low-power support through Power-Down and Idle modes
- Fully synthesizable, scan ready design
- The M8051EW+ is available in both Verilog and VHDL source RTL.
- The deliverables include:
- Verilog/VHDL source code
- Integration Testbench and Test-suite
- Comprehensive Documentation
- Constraints and Scripts for simulation and synthesis with support for common EDA tools