Overcoming the Memory System Challenge in Dataflow Processing
Wave Computing’s Dataflow Processing Unit (DPU) incorporates 16,000 dataflow processing elements (PEs). Its revolutionary dataflow architecture targets machine learning applications and requires extreme memory throughput to keep the PE pipelines fed. By adopting 3D high-speed memory in addition to conventional DRAMs, the DPU has access to over 250 GB/sec of memory bandwidth, but achieving such throughput requires spreading traffic within and across high-speed memory channels. Wave’s dataflow architecture uses the SonicsGN NoC with interleaved multi-channel technology (IMT) to maximize throughput by ensuring load balancing across the memories. IMT transparently distributes traffic to minimize performance hot spots, while providing complete flexibility on network and layout topology.
Block Diagram of the Machine Learning SOC Development and Memory Subsystem IP