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MIPI C-PHY and D-PHY Combo
The MXL-CPHY-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or MIPI Slave supporting camera interface CSI-2 v1.2 and display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-C v1.0 applications in the C-PHY mode. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
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Block Diagram of the MIPI C-PHY and D-PHY Combo IP Core
MIPI D-PHY IP
- MIPI D-PHY in TSMC (40nm, 28nm, 16nm, 12nm, 7nm)
- MIPI D-PHY DSI/CSI Transmitter IP (Silicon proven in TSMC 22ULP)
- MIPI CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
- MIPI D-PHY Universal Lane 16FFC IP for Automotive
- MIPI Universal D-PHY IP - 4.5Gbps/lane, MIPI D-PHY v2.5 Compliant