MIPI C-PHY/D-PHY Combo Receiver
The C-PHY is based on 3-Phase symbol encoding technology delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 2500 Msps per lane, which is the equivalent of about 182.8 to 5714 Mbps per lane.
The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration and up to 2500 Mbps with deskew calibration.
The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The maximum data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication.
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Block Diagram of the MIPI C-PHY/D-PHY Combo Receiver IP Core
MIPI D-PHY IP
- MIPI D-PHY in TSMC (40nm, 28nm, 16nm, 12nm, 7nm)
- MIPI D-PHY DSI/CSI Transmitter IP (Silicon proven in TSMC 22ULP)
- MIPI CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
- MIPI D-PHY Universal Lane 16FFC IP for Automotive
- MIPI Universal D-PHY IP - 4.5Gbps/lane, MIPI D-PHY v2.5 Compliant