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USB 3.1 SuperSpeed+ (Gen2) Dual-Role Device Controller (USB-IF Certified)
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MIPI C-PHY/D-PHY Combo Receiver
The MXL-CPHY-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as MIPI Slave supporting camera interface CSI-2 v1.2 and display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-C v1.0 applications in the C-PHY mode. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
The C-PHY is based on 3-Phase symbol encoding technology delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 2500 Msps per lane, which is the equivalent of about 182.8 to 5714 Mbps per lane.
The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration and up to 2500 Mbps with deskew calibration.
The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The maximum data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication.
The C-PHY is based on 3-Phase symbol encoding technology delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 2500 Msps per lane, which is the equivalent of about 182.8 to 5714 Mbps per lane.
The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration and up to 2500 Mbps with deskew calibration.
The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The maximum data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication.
Features
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI® Specification for D-PHY Version 1.2.
- Supports MIPI® Specification for C-PHY Version 1.0.
- Four Lane in D-PHY mode.
- Three Lane in C-PHY mode.
- Supports both high speed and low-power modes.
- 80 Mbps to 1.5 Gbps data rate per lane in D-PHY mode without Deskew calibration.
- Up to 2.5 Gbps data rate per lane in D-PHY mode with Deskew calibration.
- 80 Msps to 2.5 Gsps symbol rate per lane in C-PHY high speed mode.
- Equivalent to 182.8 Mbps to 5.714 Gbps per lane in C-PHY high speed mode.
- 10 Mbps data rate in low-power mode.
- Low power dissipation.
- Loopback testability support.
- Optional resistance termination calibrator.
- Deskew calibration support in D-PHY.
Benefits
- Compatible with both C-PHY 1.0 and D-PHY 1.2 specifications for added flexibility
Deliverables
- Data Sheet
- GDSII
- LVS Netlist
- Integration Guidelines
- Synopsis timing Model
- Behavioral Model
- LEF File for P&R
Applications
- Mobile
- IoT
- Display
- Camera
- Virtual Reality
- Augmented Reality
Block Diagram of the MIPI C-PHY/D-PHY Combo Receiver IP Core
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MIPI D-PHY
- MIPI D-PHY Compliant With CSI-2 And DSI
- MIPI CPHY DPHY Combo PHY IP on TSMC 16FF/12FF
- MIPI CSI-2 Tansmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC 22nm
- MIPI D-PHY 2.0Gbps (4-lanes TX/RX, PLL integrated) TSMC 16FF+LL
- MIPI D-PHY in TSMC (40nm, 28nm, 16nm, 12nm, 7nm)