The MIPI Display Serial Interface (DSI) is an interface between a Display or other data interface and a host processor baseband application engine. This interface is defined by MIPI Alliance, which defines a series of modules in a MIPI compliant product.
The MIPI DSI Receiver is used in mobile and high–speed serial applications as a controller for receiving video, command or user data transmitted using MIPI DSI Transmitter over MIPI lines. It is sent to the next higher level for subsequent processing. The MIPI DSI Receiver along with MIPI DPHY provides a complete solution for decoding MIPI DSI data.
- Compliant with MIPI DSI Standard v1.1 and MIPI D-PHY Standard v1.1
- Max 1.5 Gbps data transfer rate per Data Lane of DPHY
- Programmable 1, 2 or 4 Data Lane Configuration.
- Configurable Virtual Channel up to 4
- Operate in continuous and non-continuous clock modes.
- Command and Video Mode are supported.
- Burst and Non-Burst modes are supported.
- Pulse and Event modes supported
- Color Modes: 12, 16, 18 and 24 bpp
- Highly modular and configurable design
- Layered architecture
- Active low async reset
- Clearly de-marked clock domains
- Extensive clock gating support
- Design Guide
- Verification Guide
- Synthesis Guide
- Configurable RTL Code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
Block Diagram of the MIPI Controller DSI2 Rx IP IP Core