The MIPI D-PHY is used in mobile and high –speed serial applications where a MIPI lane is involved. The MIPI D-PHY adheres to MIPI D-PHY Specification. The The MIPI D-PHY along with the MIPI CSI Transmitter or CSI Receiver or DSI Host or DSI Slave provides a complete solution for encoding oe decoding MIPI data.
The MIPI PHY (D-PHY) specification defines an interface between the MIPI lanes and MIPI core engine like MIPI DSI or CSI. This interface is defined by MIPI consortium, which defines a series of modules in a MIPI compliant product.
- Compliant with MIPI C-PHY draft version 1.0
- Uses Trio conductors with Clock-Data Embedded.
- Encoding and Decoding of Delta_Polarity
- 16-7symbol mapper de-mapper
- PPI+ Interface
- Error Insertion and Data corruption ability.
- Axi4lite interface for register configuration.
- Scalable to any number of lanes
- All type of Lane configurability (Ex: CIL-MFAA, CIL-SFAA, etc)
- PRBS Supported
- RTL code
- Detailed design document
- Verification environment
- Test cases
- Synthesis environment/scripts
- Design Guide
- Synthesis guide