The Synopsys' DesignWare MIPI CSI-2 IP Host Controller is a fully-verified configurable digital core that is compliant with the MIPI Alliance CSI-2 Specification. This IP provided a high-speed serial interface between an application or image processor and MIPI CSI-2 compliant camera sensor. The Synopsys DesignWare MIPI CSI-2 Host Controller IP is architected to interface with the physical layer through the MIPI recommended PPI, providing easy integration to a D-PHY such as the high-quality Synopsys DesignWare MIPI D-PHY IP.
When combined with the DesignWare MIPI D-PHY IP, Synopsys provides a complete, single vendor MIPI CSI-2 solution. This solution enables designers to lower the risk and cost of integrating the MIPI CSI-2 interface into application processors, image signal processors and multimedia co-processors while improving time-to-market of mobile electronics.
Compliant with MIPI csi-2 Interface Specification, rev. 1.0
PPI interface to D-PHY
Configurable from 1 to 4 data lanes
32bit Pixel Output format
Supports all primary and secondary data formats
Low Power and Ultra Low Power modes
AMBA-APB control and configuration interface
Timing accurate signaling
Error detection and correction
coreConsultant tool for single IP configuration, synthesis and simulation (GUI or batch scripts)
Source Verilog RTL
Automated synthesis using coreAssembler/coreConsultant, including support for DFT insertion and low power synthesis