The MIPI CSI receiver IP Core is used in mobile and high –speed serial applications where a camera can send the video data using MIPI CSI Transmitter over MIPI lines to the MIPI CSI Receiver for decoding the data and use it for subsequent processing. The MIPI CSI Receiver adheres to MIPI CSI Specification. The MIPI CSI Receiver along with the MIPI DPHY provides a complete solution for decoding MIPI data.
The MIPI Camera Serial Interface 2 (CSI-2) specification defines an interface between a peripheral device (camera) and a host processor (baseband, application engine). This interface is defined by MIPI consortium, which defines a series of modules in a MIPI compliant product.
- Compliant with MIPI CSI-2 Spec v1.1 and MIPI D-PHY Spec v1.1
- Max 1.5 Gbps data transfer rate per Data Lane of DPHY
- Programmable 1, 2 or 4 Data Lane Configuration.
- Operate in continuous and non-continuous clock modes. Command and Video Mode are supported.
- Burst and Non-Burst modes are supported.
- Video Packet Formats:YUV-422 8-bit, RGB-888, RGB-565, RAW-8, RAW-10 and RAW-12
- Camera Interface: 8, 16 and 24 bpp
- Progressive Scanning
- RTL code
- Detailed design document
- Verification environment
- Test cases
- Synthesis environment/scripts
- Design Guide
- Synthesis guide
Block Diagram of the MIPI CSI Receiver