MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve throughput over bandwidth limited channel, the C-PHY is developed and is based on 3-phase symbol encoding technology delivering 2.28 bits per symbol over three-wire trios.
- Fully compliant with MIPI D-PHY spec up to v1.2 (by different process nodes)
- Supports MIPI DSI-1 and CSI-2 protocol
- Supports HS data rate from 80Mbps up to 2.5Gbps (per lane)
- Supports LS data rate of 10Mbps and Ultra-low power mode
- Supports 1 clock lane & up to 4 data lanes
- Provides extremely energy-efficient mode (<10mA per IP)
- Provides a stand-alone BIST module for mass production test