The MXL-DPHY-DSI-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY.
The IP can be configured as a MIPI Master optimized for display (DSI) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
- Consists of 1 Clock lane and up to 4 Data lanes
- MIPI DPHY V1.1 specifications
- Supports both high speed and low-power modes
- 80 Mbps to 800Mbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Serializers and Deserializers included
- Low power dissipation
- Loopback testability support
- Optional resistance termination calibrator
- LVS netlist
- LEF file
- Verilog Model
- Timing Model
- Integration Guidlines
- One year support
Block Diagram of the MIPI D-PHY Transmitter IP Core