The demand for advanced multimedia features is pushing device manufacturers to integrate more advanced peripherals such as multi megapixel cameras and larger screens. Integrating these capabilities into next-generation devices brings new challenges to the industry in terms of power, time-to-market and overall system costs.
To address these challenges, the Mobile Industry Processor Interface (MIPI®) Alliance defines and promotes open interface specifications, such as the Camera Serial Interface (CSI-2), Display Serial Interface (DSI), which all use the MIPI D-PHY.
As a MIPI Alliance contributor and leading provider of interface and analog IP, Synopsys offers a high-quality, silicon-proven D-PHY IP solutions that are available today in advanced process technologies.
Low-power (LP) escape modes and ultra low-power state (ULPS) modes
SCAN and loopback BIST modes
Extensive access to internal programmability registers
Mater, Slave, Tx-only and Rx-only configurations
Attachable PLL for master applications; Flexible input clock reference
50% DDR output clock duty cycle
Silicon-proven, robust design available in advanced process technologies
Compliant with the MIPI D-PHY Interface Specification, rev. 1.2
Fully integrated hard macro; Up to 2.5 Gbps per lane
Aggregate throughput up to 10 Gbps in 4 data lanes
Supports PHY Protocol Interface (PPI)
GDSII Layout Database
Video Demo of the MIPI DPHY Gen2 Bidirectional 4 Lanes - TSMC 16FFPGL, FFPLL 1.8V, North/South Poly Orientation