UFS is a simple, high performance, serial interface used in mobile systems as a mechanism to communicate between host processor and mass storage devices like Flash and other non-volatile memories. This communication is achieved using a UFS Host and UFS Device, using MIPI Unipro and MPHY as Link and PHY layers respectively. UFS Host controller interface is responsible for managing the interface between host software and UFS device to do a data transfer. It also does the interface management, power management and control.
The UFS Host device works perfectly with the UFS Device, GDA MIPI Unipro and our Partner's MPHY. With this, we provide the complete solution including software.
UFS host registers are programmed by system software using AHB slave interface.AXI Master Interface is used by the DMA engine to fetch the Command, Query, and Task Management UPIU’s, Data for the DataOut UPIU’s available in system memory for TX transfers and AXI Master Interface is used by DMA engine to store the Response UPIU’s
and data received by DataIn UPIU’s into the system memory.UTP engine controls the UPIU encoding and decoding. UniPro interface controls the data transfer through CPORT and also controls DME through the UIC registers programmed by system software.
- Complaint with UFS 1.0 spec, UFS Host Controller Interface V1.0, MIPI UniPro V1.41, MIPI M-PHY spec v2.0.
- M-PHY LS and HS data rates HS1X, HS2X supported.
- .[3Gbps-6Gbps per lane in HS mode]
- Supports configurable outstanding commands/Query request UPIU for UTP layer in UFS device.
- Supports 32 UTP Transfer request descriptors and 8 UTP Task Management Descriptors for UFS host.
- AXI3 and AHB used for easy integration into SOC
- RTL code
- Detailed design document
- Verification environment
- Test cases
- Synthesis environment/scripts
Block Diagram of the MIPI UFS Host IP Core