The Digital Blocks DB-RTP-UDP-IP-MPEG-TS IP Core contains a MPEG Transport Stream (TS) processor with RTP/UDP/IP Protocol Hardware Stack, MAC Layer Pre- & Post-Processors, and an ARP Packet Processor targeting high packet throughput or low latency of MPEG Transport of Audio/Video Packets over a Internet Protocol (IP) Network or storage in memory. The DB-RTP-UDP-IP-MPEG-TS is a Verilog SoC IP Core targeting Xilinx/Altera/Lattice/Microsemi FPGAs and ASIC/ASSP devices.
- Compliance with ISO/IEC 13818-1
- MPEG Transport Stream with programmable RTP Encapsulation (Transmitter) / Decapsulation (Receiver) over UDP/IP Protocols.
- 10/100 Mb & 1/10/40 Gb wire-line performance with ultra-low latency
- MPEG-TS Optional Configurations:
- 1, 2, 4, 8, 16 MPEG Transport Streams
- Encapsulation / Decapsulation for both Transmit & Receive
- Either Encapsulation or Decapsulation for reduced VLSI footprint
- Address Resolution Protocol (ARP) Packet Processor (client/server)with 4-16 entry ARP cache
- Internet Protocol (IP) Packet Processor:
- Support for both IPv4 and IPv6 protocols
- IP & ICMP (Internet Control Message Protocol) Protocol
- Host IP address filter, IP header checksum check & generator, user selectable Maximum Transmission Unit (MTU), Unicast & Multicast Packet support
- User Datagram Protocol (UDP)Packet Processor:
- Support for up to 16 UDP Ports
- UDP header checksum check & generator
- Real-time Transport Protocol (RTP) Packet Processor
- Encapsulates/Decapsulates MPEG-TS to RTP packets
- Compliant with RFC 3894 and RFC 6184
- High Speed Data Interface to user Host Application
- PHY Controller – control interface to user Host Application
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Block Diagram of the MPEG Transport Stream with RTP / UDP / IP Hardware Stack