The Multi-Link Gearbox (MLG) functionality is defined by the OIF Multi-link Gearbox Implementation Agreement (OIF-MLG-01.0, May 2012).
The MLG interface multiplexes ten 10GBase-R PCS channels into a single 100Gbps link compatible with the IEEE 802.3ba Clause 82 100Gbps Ethernet CAUI-4 interface.
On Transmit, the MLG Core creates a datastream of 20 VLs (Virtual Lanes), adds the MLG markers and bit-muxes the VLs into four 25G Serdes interfaces.
On Receive, the MLG Core performs bit demuxing, lane alignment, marker termination and VL reordering to recreate 10 independent 10GBase-R streams.
To compensate for the bandwidth overhead from the MLG markers insertion, the Core, on Transmit, removes XGMII Idle columns, on each 10GBase-R stream.
The Core implements the ten 10GBase-R PCS functions and provides per channel a 32-bit XGMII for direct interconnect with 10G Ethernet MACs.
For management and configuration a 16-Bit de-multiplexed register interface allows accessing each individual channel. The core is delivered in generic Source Verilog synthesizable HDL code and is provided with a comprehensive verification environment.
- MLG Functions
- Compliant with the OIF MLG-01.0 specification
- Encoded and scrambled 10GBase-R PCS stream muxing / demuxing into / from 20 VLs (Virtual Lanes)
- Multi-Lane Distribution (MLD) across 20 Virtual Lanes
- Implements Lane deskew and realignment.
- Periodic MLG Alignment Marker insertion / striping on transmit / receive
- Performs BIP-8 (Bit Interleaved Parity) insertion and checking according to IEEE Std 802.3ba specification
- PMA interface width programmable to 32, 40 or 64 Bits with a synthesis parameter
- Interoperable with a large variety of 25.78125 Gbps Serdes solutions
- 10GBase-R PCS Functions
- Compliant with the IEEE802.3 Clause 49 and Clause 51 specification and UNH tested
- Implements Ethernet 64/66b data coder / decoder scrambler and block synchronization
- Supports Clause 49 reserved codes.
- Implements Test Pattern Generator/Checker
- Rate adaptation with XGMII columns Idle insertion and removal
- Implement Bit Error Rate (BER) monitoring, with high error rate indication, providing constant line quality monitoring
- Media independent 32-Bit non-DDR XGMII Interface to the MAC
- Can be seamlessly connected to MorethanIP silicon proven 10Geth MAC Core
- Management Interface
- Simple 16-Bit demultiplexed register interface
- Includes standard 10Geth PCS MDIO Manageable Devices (MMD) register space for each 10GBase-R channel
- Extended MLG management and statistic registers implemented
Block Diagram of the OIF MLG (Multi-Link Gearbox) 1.0 Core IP Core