The Xelic Optical Transport Network (OTN) ODTU23 Multiplexer Core (XCO23MX) performs tributary timeslot interleaving of four independent ODU2 data streams and maps them into an ODU3 or OTU3 frame structure. OPU3 multiplex overhead is inserted and automatic justification control is provided based on programmable FIFO thresholds or incoming PJ/NJ request signaling. Incoming line side OPU3 overhead is interpreted with error and justification detection reported. System side ODU2 frames are transferred using four separate 64-bit data bus ports operating at a clock rate up to 168.04MHz. Line side data is transferred at an OTU3 rate using a 256-bit data bus operating at 168.04MHz or at an ODU3 rate using a 256-bit data bus operating at 157.50MHz.
The XCO23MX Transmit Processor contains four FIFO’s with upper threshold, lower threshold, and overflow/underflow detection. Justifications (positive and negative) for each ODU2 data stream are performed (including both single and double positive justification capability) through a transmit OPU processor. OPU3 overhead insertion includes Payload Structure Identifier (PSI), justification overhead and reserved fields. PSI field insertion consists of payload type, multiplex structure identifier, and reserved bytes multi-frame information. A test mode is available to insert PRBS data into any of the 4 ODU2 frame timeslots. ODU2 frames are mapped into either ODU3 frames or OTU3 frames with blanked FEC. Generated ODU3/OTU3 frames contain blanked OTU3 and ODU3 overhead. FAS and MFAS information is inserted into outgoing frames in addition to OPU3 overhead.
The XCO23MX Receive Processor contains a frame position counter synchronized to incoming FAS and MFAS frame indicators. OPU3 overhead is extracted from incoming frames and interpreted with various error conditions reported to an internal maskable interrupt register. Positive (single and double) and negative justifications are detected and reported though output signaling and internal interrupts. Tributary timeslot deinterleaving is performed on incoming frames and ODU2 frames are de-mapped and delivered to four internal FIFO structures. Configurable depth FIFO’s are implemented for each system side ODU2 signal interface.
Performance counters (configurable for interval count capture) are provided for the accumulation of inserted (XCO23MX transmit processor) and detected (XCO23MX receive processor) positive and negative justification events. Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCO23MX provides facility and terminal loopback modes of operation using Transmit and Receive Processor data path configurations for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCO23MX core available under flexible single use licensing terms with netlist or source code deliverables.
- Implements 16-bit register interface for programming of internal registers.
- Complies with ITU-T G.709 and ITU-T G.798 specifications.
- Supports transmit and receive facility and terminal loopback configurations.
- Accepts 4 independent ODU2 frames and performs tributary timeslot interleaving.
- Provides independent configurable FIFO’s for each ODU2 data stream.
- Provides justification control capability through FIFO threshold levels or incoming PJ/NJ request signaling.
- Supports justification corruption capability through internal register programming for test purposes.
- Inserts FAS/MFAS framing information with output signaling provided.
- Provides saturating counters for positive and negative justifications detected with programmable latch and clear or incoming error sync capture configurations.
- Optionally inserts PRBS data insertion into any timeslot for test purposes.
- Generates ODU3 or OTU3 frames with blanked ODU3 overhead and FEC (OTU3 frames).
- Interprets and extracts incoming OPU3 overhead information and reports errors to internal register with maskable interrupt capability.