The PCI Express Endpoint Controller is a highly flexible and configurable design targeted for end-point implementations in desktop, server, mobile, networking and telecom applications. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint.
The PCI Express Endpoint Controller is part of PCI-Express (GPEX) family of IP solutions which includes Root Complex (GPEX-RC), Hybrid (GPEX-HY), Switch port Controller (GPEX-SW), Switch (GPEX-SWITCH), GPEX-AXI Bridge (GPEX-AXI), GPEX-AHB Bridge (GPEX-AHB) and Advanced Switching (GPEX-AS) designs.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications. Mobiveil solution provides highly scalable bandwidth through configurable lanes, widths and frequencies.
The PCI Express Endpoint Controller leverages Mobiveil’s years of experience in PCI, PCI-X and HyperTransport technologies and the expertise in creating system validated IP solutions with RTL, synthesis, simulation, board and software elements to offer lowest risk in terms of compliance and inter operability.
- Compliant to PCI Express base specification version 4.0,
- 4.0 and backward compatible with PCI Express versions 3.0, 2.0 and 1.1
- Supports SR-IOV and complaint to Single Root I/O Virtualization and Sharing Specification Revision 1.0
- Compliant to Address Translation Services Revision 1.0
- Supports configurable number of PFs and VFs for SR-IOV
- Architected for high link utilization and low latency
- Efficient receive and transmit-retry buffering scheme
- Completely handles PCI-Express ordering rules
- Implements flow control logic in both directions
- Packet oriented user logic interface
- Supports PIPE 3.0 Compliant PHYs
- Flexible lane ordering and support for lane reversal
- Superior architecture-optimized for high performance, link utilization, low latency, low power and low gate count
- Feature rich, highly flexible, scalable, configurable and timing friendly design
- Ease of integration
- Verified with leading VIP
- Verilog RTL
- Behavioral test bench and test cases
- PCI Express and Application BFM
- ASIC Synthesis environment
- PC’s workstations and servers
- Flash Storage
- Networking and communications
- General purpose system chip interconnect for any compute platform
Block Diagram of the PCI Express Gen1/Gen2/Gen3 End point Controller with SRIOV Support