Implements all the required protocol features
IP has OCP interface for connecting to the System Bus
IP core verified with Denali's Pure Spec™ Verification IP for PCI express through extensive simulations and functional coverage methodology.
Verification environment in Specman's 'e' language with coverage reports.
Validated on Xilinx Virtex4 FPGA
IP core tested with Catalyst PCI express compliance kit.
Proven on a product prototype chip (90nm Technology) for one of our steemed customer.
Customized for bulk data transfer.
- PCI Express Base Specification v1.1 compliant
- PIPE Specification v1.0 compliant
- Configurable as Root Complex or End Point
- Supports memory, configuration and message transactions
- Supports end-to-end cyclic redundancy code (ECRC) generation/checking
- Supports advanced error reporting (AER)
- Max Payload Size from 128 to 512 bytes
- Supports two Virtual Channels
- Supports Device Serial Number capability
- 32-bit data path width
- Core operates at 125 MHz with 16-bit PIPE interface
- Supports system side clock frequency of 50 - 200 MHz
- Integrated 2-channel DMA on receive path
- Complete link training (LTSSM), including loop back master support
- Support for device power management states (D0, D3 Hot and D3 Cold)
- Supports beacon signaling for wake up mechanism
- IP has OCP interface for connecting to the System Bus
- Proven on a product prototype chip (90nm Technology) for one of our steemed customer
- Verilog RTL
- Specman based verification environment
- Synthesis and STA scripts
- Register Description Document
- User Guide