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Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline
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PCIe 3/2/1 SerDes PHY
The Rambus 12 Gbps PCIe SerDes PHYs is a general-purpose, high-speed serial link transceiver subsystem that support data rates from 1.25 Gbps to 12 Gbps. Optimized for power and area in high-loss channels, our 12G MPS PHYs are suitable for a broad range of enterprise-class systems.
Features
- Duplex lane configurations of x2, x4, and x22
- Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
- Support for AC-coupled interfaces
- Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
- BER of 10-15 for CEI11-LR/SR and BER of 10-12 for SFI, XFI, PCIe and Gbe protocolsA wide range of PLL multiplication supporting low reference clock frequenciesTight skew control of 2UI between lanes of the PMABuilt-in Self Test (BIST) with ATPG and AC/DC boundary scan supportBuilt-in PRBS pattern generation and checking for standalone loopback testingContinuous time linear equalizer (CTLe) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
Deliverables
- PMA Hard Macro
- PCS-BIST Soft Macro
- Datasheet
- SoC integration guide
- Optional design integration and bring-up support services
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