The Video and LCD Controller IP Core interfaces to a PLB V4.6 bus for reading video data and for register access. The core can control both passive and active (TFT) LCD displays as well as provide video data and timing for VGA and DVI interfaced displays. The IP core is intended for Xilinx based embedded FPGA designs.
- Supports PLBv4.6 bus
- PLB bus master port width of 32 , 64 or 128 bits
- Selectable pixel FIFO depths of 256, 512 or 1024 words.
- Controls both passive and active LCD displays
- Passive displays can have 4096 colours using random frame rate modulation.
- Controls VGA monitors
- Includes optional PWM and GPIO channels for back light, contrast and display on/off control
- Frame synchronous base address reload to allow gaming displays.
- Frame interrupt signal for software synchronisation.
- Supports from 1 to 32 bits per pixel resolution
- Supports high-resolution display modes
- Separate pixel and system bus clocks
- Configurable small footprint core
- Flexibility, small footprint
- Netlist, documentation, reference design
Block Diagram of the XPS Video and LCD Controller IP Core