XPS Video and LCD Controller IP Core

The Video and LCD Controller IP Core interfaces to a PLB V4.6 bus for reading video data and for register access. The core can control both passive and active (TFT) LCD displays as well as provide video data and timing for VGA and DVI interfaced displays. The IP core is intended for Xilinx based embedded FPGA designs.

• see the entire PLB Bus Based Video Controller datasheet
• get in contact with PLB Bus Based Video Controller Supplier