Solomon codes, a class of error correction codes, are block-oriented coding schemes used in communication systems for FEC (Forward Error Correction). Information coding prior to transmission is performed against limited transmit power/bandwidth. ReedSolomon decoding architectures contribute to systems that are sensitive to transmission errors, with no data acknowledge or data retransmit. They are well suited for correcting errors that occur in bursts. Combined with a Viterbi coding scheme, ReedSolomon codes can be used to create concatenated code with increased performance.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
- Error and erasure decode supported
- Decode puncturing schemes supported
- Automatic configuration provided for widely recognized and applied RS coding standards
- Multiple channel optional embodiment
- CCSDS support
- Frame lengths may vary within a valid range
- Symbol clock rate is allowed to be specified, defining a system/symbol clock rate ratio
- Internal buffering allows the blocks to be continuously fed into the core
- Block length value user-configurable
- The number of information/check symbols transmitted user-configurable
- Symbol width user-configurable
- GF primitive polynomial user-configurable
- Optional port may be configured supporting erasure decode status outputs
- Optional port may be configured to monitor both originally received and decoded data
- Optionally configured synchronous reset and clock enable and dedicated ports
- Optional port profile automatically adjusted against the core functional profile selected
- Core customization against the application requirements supported by parameterized, flexible IP core implementation
- Single clock synchronous design
- Technology independent HDL code
- SoC integration support
- Core configuration/customization support
- Reed-Solomon decoder IP core delivers technology independent, structural HDL design that can be applied to a set of industry standards handling error correction schemes.
- Functional IP core profiling against the predefined set of optional core features, end application specification alignment.
- Reed-Solomon decoder IP core Verilog source code
- Reed-Solomon decoder IP core VHDL source code, if this option is selected by the customer
- The set of configuration files
- Reed-Solomon code configuration
- IP core functional profile
- IP core boundary configuration
- CCSDS, IEEE-802.16, ATSC, DVB automatic configuration support
- The IP core test environment developed in Verilog HDL.
- Documentation :
- Architecture specification
- Microarchitecture (RTL) specification
- TC definition document
- Testbench structure document
- SoC integration dedicated information
- Referent Reed-Solomon decode algorithm C implementation, if this option is selected by the customer.