The Reduced Latency DRAM (RLDRAM) 3 Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.
The core has been optimized to take advantage of the fast random cycle and fast access times available with RLDRAM 3. The core also supports both multiplexed and non-multiplexed addressing.
The core accepts commands using a simple local interface and translates them to the command sequences required by RLDRAM 3 devices. The core also performs all initialization and refresh functions.
The core is provided with run-time programmable inputs for all memory timing parameters and configuration settings. This ensures compatibility with all RLDRAM 3 configurations. Add-On Cores such as a Bus Interface, Multi-Port Front-End etc. can be optionally delivered with the core. The core is delivered fully integrated and verified with the target DDR PHY.
- Achieves high clock rates with minimal routing constraints
- Supports quarter-rate clock operation
- Supports multi-bank refresh
- Supports multiplexed and nonmultiplexed address interface to RLDRAM 3 devices
- Supports x18, and x36 devices in any combined data width (18, 36, 72, etc.)
- Multi-channel interface available where multiple requests can be accepted on each local clock
- Full run-time configurable timing parameters and memory settings
- Full set of Add-On Cores available
- Delivered fully integrated and verified with target DDR PHY
- Minimal ASIC gate count
- Broad range of ASIC and FPGA platforms supported
- Source code available
- Customization and Integration services available
Block Diagram of the RLDRAM 3 Controller Core IP Core