VSORA’s IP is based on a revolutionary DSP architecture and design-methodology that provide superior utilization, performance, area and power over many existing solutions. VSORA DSPs possess a scalable memory-bandwidth to meet the processing power needed by AI, 5G and Edge computing, and do not rely on the support of co-processors, which add area and consume additional power. VSORA’s solution offers remarkable productivity gains and accelerates time-to-market via a high-level development flow ideal for algorithm development, without requiring development of low-level implementation code. The architecture is completely scalable, from single to multi-core solutions, to best suit specific requirements.
- DSP architecture is based on the concept of scalable computation units called Matrix Processing Units (MPUs) available in two versions (see datasheet):
- MPU 801 – Contain multiples of 8 Real ALUs, or 4 Complex ALUs.
- MPU 3201 – Contain multiples of 32 Real ALUs, or 16 Complex ALUs.
- Customizable DSP-processing power
- Customizable Floating-point Arithmetic Logical Units
- Efficient low power instructions
- High processing-power eliminates the need for specific coprocessors and ensures greater flexibility
- High level description of algorithms