Scalable Video Processor
The block can be configured for up to eight video channels, which may be of different video standards. Each of these inputs can be de-interlaced and resized, then composited onto the video output. Each video output can comprise a single video input or a composite multi-view of multiple video inputs, facilitating quad-split display, etc.
The OSVP block has been optimised for Xilinx FPGA technology and achieves the highest broadcast quality video processing in an extremely small footprint IP core.
A series of reference designs are available called RTVE (Real Time Video Engine). These designs integrate the OSVP IP with Xilinx VIPP in a complete working FPGA design targeted for a range of hardware platforms.
Features
- Chroma resampling
- De-interlacing
- Resizing
- Composite onto video output with graphic overlay
- Video resolutions up to 2048x2048
- YUV and RGB colour in 4:2:2 or 4:4:4 format
- 8, 10 or 12 bit colour depth per plane
- Interlaced, progressive and progressive segmented frame (PsF) support
- Motion and low angle edge adaptive de-interlacing
- 3:2 and 2:2 film cadence detection and processing
- Detail enhancement
- Configurable resizer taps (2 to 64)
- Video frame rate up to 120Hz
- Asynchronous input and output timing with frame synchronization capability
- Provides frame synchronous transitions when changing video standards
- Video graphic overlay support
- AXI4-MM interface to SDRAM controller
- AXI4-Lite interface to control registers
- AXI4-Stream for Video interfaces
Applications
- Flat panel display controllers
- Broadcast Monitors
- Format conversion
- Medical Imaging
- Security Monitoring
- Multi-viewer displays
Block Diagram of the Scalable Video Processor IP Core

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