Shared Multi Memory Integration Controller is a memory controller with option to have more masters connected to access a memory. And on the memory side, it enables user to connect more than one memory clubbed together to make a bigger memory. In this way smaller memory segment are created to enable users to make much bigger memory system. This system has much higher data rate and same memory can be accessed by multiple masters.
- Multiple Slave side interfaces supported configurable for each port.
- Standard AMBA interfaces AXI, AHB and APB Supported.
- All Transfer types are Supported.
- Narrow Write Transfers are supported.
- Multiple Memory of Same Size can be connected to the SMMIC.
- Multiple options for End-to-End data protection across SMMIC are supported.
- Multiple Options for End-to-End data protection across memory are supported.
- Narrow Write Transfers are supported with local read-modify-write operations.
- Runtime Arbitration Selection to optimize routing and memory usage based on transaction profiling.
- Low Latency System. Write and read delay of 2 clocks for first transfer. Throughput of 100% if no Data Congestion.
- Intelligently architecture for Low Data Congestion.
- Place and Route Friendly even on large number of masters and memories.
- Low in Gate Count.
- Port Arbitration and Priority –
- Intelligent bandwidth based arbitration.
- Fixed Mode.
- Round Robin Mode.
- Mixed Mode.
- Power Consideration done in place –
- Low Toggling internal command and control structure.
- Clock Gating options.
- Power Down and low voltage options for specific unused section.
- UPF Compliant Low Power Option.
- Snooping options available with snooping filters.
- Tracing Compliant to ARM ATP Compliance.
- Transaction Profiling options.
- This IP is MAJOR ADVANCEMENT. The major difference is its
- Latencies which are bought down by intelligently architecting
- the complete design. Routing Congestion is totally removed by
- developing it in a way that Multistage Hierarchal Mux does not
- bring all the ports at the same location. Data Coherency issue
- resolved in hardware by intelligent architecture.
- The solution is best suitable for making high Performance SOC’s
- which are built for very low reaction time and Very High
- Memory bandwidth memory operation. SOC which have
- planned Market segment of Applications like Cloud AI/ ML, Edge
- AI, Big Data Analysis, Automotive, Embedded Vision, Real Time
- Application, IIOT, Autonomous Engineering, and Robotics are
- the best candidate to use this IP into their SOC.
Block Diagram of the Shared Multi Memory Integration Controller IP Core