Silicon proven Viterbi decoder for UWB 802.15

Features

• K=7 (64 states) G0=171(octal), G1=165(octal), G2=133(octal).
• Rate 1/3. Other rates can be supplied by external puncturing.
• radix 4 algorithm.
• Throughput of 480 Mbit/sec and higher.
• Supports partial zero tail bits (only 4 zero tail bits to partial closing of the trellis path).
• Parameterizable input soft width.
• Parameterizable traceback length (memory depth).
• On the fly configurable traceback length, to support low latency.
• Zero delay between packets.
• Supports low power features.
• Area/Power efficient architecture utilizing RAM for trace back storage
• All-synchronous design using a single clock, except for global asynchronous reset.
• Available as verilog source code or as netlist.
• Silicon proven

Benefits

• Silicon proven with 528Mbps on 0.13 micron general purpose technology

Deliverables

• Verilog source code or verilog EDIF netlist.
• Verilog testing environment
• Bit-exact Matlab model
• Documentation.