Single precision floating-point parametrized multi operands square sum with fast speed (only 6 clock-cycles of latency).
- Synthesizable, technology independent Verilog HDL Core.
- 32 bits floating-point arithmetic.
- IEEE 754 compliant.
- High-speed fully pipelined architecture.
- Only 6 clock-cycles of latency.
- Max operands 4, it can be defined 1-4 as you like.
- (1).Faster speed
- (2). Parametrized multi operands.
- (1). Floating-point pipelines and arithmetic units.
- (2). Floating-point processors.