The EFLX®150 is an embedded FPGA IP core, for implementing reconfigurable logic, containing 96 Look-Up-Tables (LUTs: each is a 6-input LUT with 2 independent outputs and 2 bypassable flip flops, equivalent to ~150 LUT4s) in Reconfigurable Building Blocks (RBBs), patented XFLX™ interconnect network, clock & scan: reconfigurable at any time. There are 224 input pins and 224 output pins.
The EFLX150 Core comprises of three major blocks: the reconfigurable building blocks (RBBs), the interconnect network, and the user I/Os. EFLX features full connectivity inside the core, and provides ArrayLinx™ interconnects at the boundary to concatenate multiple cores into EFLX arrays up to 5x5 EFLX150 cores (max array ~3.7K LUT4s). It is possible to route to pins even within the array.
Single stage logic operates up to 1GHz worst case depending on the complexity of the logical operation.
The GDS for TSMC16FF+/FFC is compatible with TSMC12FFC with only the timing re-run.
- 6 metal layers - compatible with almost all metal stacks.
- All TSMC nominal supply voltages supported.
- Just 0.05mm2.
- 640 total flip flops/core.
- DFT: test vectors supplied.
- Verilog netlist with SDF timing annotation.
- GDS-II of the array.
- CDL/Spice net list.
- Complete documentation including integration guidelines.
- Integration assistance.
- Test vectors.
- EFLX Compiler with multiple PVT corners.