NetSpeed Orion represents a new way of designing and optimizing SoC interconnects.
One that takes high-level system requirements from on-chip bandwidth & latency to Quality of Service (QoS) and constructs an optimized NoC solution.
- Physically Aware, Adaptable NoC
- NetSpeed Orion is placement aware and allows full heterogeneity in NoC topology.
- The final NoC can be a ring, bus, tree, mesh or other topology.
- It adapts to floorplan as well as connectivity between components.
- Algorithmic, Sophisticated NoC
- NetSpeed Orion uses sophisticated algorithms to solve complex SoC issues like QoS & deadlock avoidance.
- It presents elegant solutions to tradeoffs between performance metrics like bandwidth, latency & power.
- Power Efficient NoC
- NetSpeed Orion is efficient in handling power, performance tradeoffs prevalent in SoC designs.
- It packetizes data and performs traffic-based optimizations optimizing every router, buffer and wire in the NoC.
- It also provides SoC architects with advanced low-power techniques like activity-based clock gating & power islanding.
- Tbps of on-chip bandwidth
- The underlying hardware elements are designed for supporting higher throughput – Terabits per second – with low footprint. Using these elements, efficient NoC can be built for variety of SoCs - from mobile to enterprise computing & networking.
- Faster Time-to-market
- NetSpeed Orion bridges the front-end & back-end design gap. It allows for more design iterations & refinement throughout design cycle. NetSpeed Orion is also correct by construction, significantly reducing debug time.
- Lower Power
- NetSpeed Orion's optimizations architecturally reduce power in NoC. It uses packetized data for communication reducing number of wires. It supports activity-based clock gating & power islanding.
- NoC Solution Platform
- NetSpeed Orion's unique heterogeneous architecture allows it to deliver scalable high performance with increasing number of IP blocks in a SoC. This allows for Orion to be used as a NoC platform for an entire product family.
Block Diagram of the Software Configuration On-Chip Network IP IP Core