The Xelic SONET/SDH Channelized High Order Path Processor Core (XCS12PP) performs path overhead processing and pointer processing for any mix of SONET/SDH payloads ranging from a granularity of STS-1 to STS-12c including non-standard concatenation types. The XCS12PP contains independent transmit and receive processors with dedicated external path overhead ports and a generic register interface to provide flexible insertion and extraction capability. Incoming/outgoing data is transferred at an STS-12/STM-4 rate using an 8-bit data bus operating at 77.76Mb/s.
- Suitable for FPGA and/or ASIC implementations.
- Supports bypass and normal (path overhead processing/pointer processing) modes of operation.
- Implements 16-bit register interface for programming of internal registers.
- Supports path and pointer processing for channelized payload types.
- Provides transmit facility and terminal loopback options for diagnostic purposes.
- Inserts high order path overhead through internal register programming and/or an external overhead port.
- Provides automatic path REI insertion (bit or block mode options) for B3 parity errors detected in the Receive Processor.
- Allows for the insertion/extraction of programmable 1, 16 or 64 byte trace messages.
- Extracts high order path overhead information to internal register locations and an external path overhead port.
- Includes 16-bit saturating performance counters (configurable for bit or block type) for the accumulation of B3 errors with programmable threshold capability.
- Provides optional interrupt generation for B3 error, signal degrade (SD) and signal fail (SF) detection.
- Provides pointer interpreter functionality with programmable state machine operation including the 8 of 10 pointer objective and single AIS state transition options for flexible configurations.
- Detects and accumulates pointer interpreter or pointer generator increments, decrements, and NDF events.
- Interprets incoming path RDI overhead information (provides programmable accept and unstable counts) and provides detection of RDI-P, ERDI-P, and path RDI unstable errors with maskable interrupt capability.
- Interprets incoming multiframe information and reports LOM errors through an optional maskable interrupt.
- Xelic cores are optimized to keep resource utilization low enabling designers to include more functionality in a single FPGA implementation.
- Xelic offers flexible licensing terms with single use, source code options available.
- Xelic cores come complete with a database which contains a verification environment (generators, checkers, models, etc), an extensive suite of self checking tests, synthesis scripts, and a comprehensive set of core documentation (product brief, datasheet, fact sheet, etc.).