Sonics3220 solution is a non-blocking peripheral on-chip network that guarantees end-to-end performance by managing data, control and test flows between all connected cores. Providing low latency access to a large number of low bandwidth, physically dispersed target cores, Sonics3220 uses a very low die area structure that facilitates a rapid path to simulation. The Sonics3220 handles incoming traffic from up to four initiators and can distribute those communication requests and responses to up to 63 targets.
By eliminating blocking, Sonics3220 allows multiple transfers to be in flight at the same time while producing a more predictable performance model for cores on a Sonics3220 system. Core service requests can occur whether there is an ongoing transfer or not. In addition, because the Sonics3220 is non-blocking, there is no need for a multi-layered bus architecture, thus reducing costs and power consumption.
Sonics3220 supports the industry standard Open Core Protocol (OCP) and AMBA Peripheral Bus (APB) interfaces.
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- Increases SoC Performance
- Isolate slow-speed I/O from high-speed SoC networks and consolidate I/O traffic to and from the SoC on-chip network
- Deterministic response supports real time applications
- Built in security feature provides hardware firewall for system and media integrity
- Shorten Time to Market
- Pre-verified configurable solution already proven to interoperate with other high speed network solutions
- Rapid integration of many IP cores spread across a die
- Pre-characterized on-chip network eliminates timing closure uncertainties
- Reuse of cores through easy configuration with a high degree of automation
- Lower Power Consumption
- Low power physical structure
- Fine granularity power management
Block Diagram of the Sonics3220 - Non-blocking peripheral on-chip network guarantees end-to-end performance