The SonicsLX on-chip network offers SoC designers a configurable system IP block designed for the creation of complex on-chip connectivity between cores. SonicsLX offers designers a balanced solution which couples low-power and tuned area, while maintaining high performance.
SonicsLX utilizes state-of-the-art physical structure design and advanced protocol management to deliver guaranteed high bandwidth together with fine grained power management. Employing both a full or partial crossbar bus structure, the SonicsLX provides low latency paths between high-bandwidth master and target IP cores.
SonicsLX Schematic supporting industry-standard interfaces (including AIX3/4, OCP2/3, AHB/APB) to the IP cores that make up an SoC. Cores connect to agents within SonicsLX that decouple the functionality of each IP core from the communications network required among the cores, adjusting for mismatches in data width, clock frequency, and protocols.
Designers can easily tailor the communications characteristics of each specific core and balance the requirements of latency, physical span, clock frequency usage, die area, and power consumption for the entire system.
Through extensive power management capabilities, SonicsLX provides low idle power and efficient use of active power, especially important for mobile phone and tablet devices.
Fine-grained power management hardware and software interfaces restrict activity to only the engaged portions of the SoC and the corresponding parts of the SonicsLX interconnect. Coarse grained clock gating pushes clock gating higher up the clock tree, saving additional power.
Key Words: ddr, ARM, network, NoC, SoC, system, ddr2, ddr3, memory, bandwidth, dram, dsp, flash, ocp, phy, wimax, lte, video, hd, ddr controller, sdram, processor, fpga, automotive, ahb, axi, amba, ddr phy, tsmc, memory controller, RAM, wifi, stb, channel, memory access, traffic, memory traffic, wireless, ip, embedded, on-chip, communications
- Easily balance performance with power and area requirements
- Optimized interconnect provides advanced features with low gate count
- Small generated logic clusters ease maximum SoC core packing
- Low power for maximum battery life
- Simplify complex SoC designs
- Universal Connectivity: Seamless connection to OCP, AHB, and AXI based cores
- Full user control of latency, performance, and area
- Robust development tools with preconfigured SoC templates speed time-to-market
- Sonics expertise helps speed time-to-market and ensures quality
- Unique design methodology eases timing closure and speeds design iteration cycles
- Integrated performance analysis tools rapidly uncover design hotspots for quick recovery
- World-class engineering support for first-time-right silicon
Block Diagram of the SonicsLX - Designers can couple low power with low cost that is tuned for optimal area