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UDP/IP Hardware Protocol Stack - 1G/10G/40G/100G - Receiver
The Digital Blocks DB-UDP-IP-RX IP Core is a UDP/IP Receiver Protocol Hardware Stack with MAC Layer Pre- & Post-Processors and an ARP Packet Processor targeting low latency UDP/IP Packet Processing. The DB-UDP-IP-RX is a Verilog SoC IP Core targeting Xilinx / Altera / Lattice / Microsemi FPGAs and ASIC / ASSP devices
Features
- 1G/10G/40G/100G Gb wire-line performance with ultra-low latency
- Address Resolution Protocol (ARP) Packet Processor (client/server) with 4-16 entry ARP cache
- IP Packet Processor:
- IP & ICMP (Internet Control Message Protocol) Protocol
- Host IP address filter, IP header checksum processing, user selectable Maximum Transmission Unit (MTU), Unicast & Multicast Packet support
- UDP Packet Processor:
- Support for up to 1-16 UDP Session, scales to 16K
- UDP header checksum processing
Deliverables
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
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