sureCore’s Low Power SRAM IP has been developed for leading-edge devices demanding long battery life and minimal operating and stand-by power consumption. PowerMiser products have been realized in both 28nm FDSOI and 40ULP BULK CMOS manufacturing processes.
This Low Power macro operates in an extreme low voltage range of 0.7v to 1.2v where it demonstrated dynamic power savings exceeding 50% of current commercial instances. The IP has also demonstrated leakage power savings ranging from 38% to 21%, depending on current conditions, while incurring only a small 10% area penalty.
The compilers supports capacities up to 576Kbit with word lengths up to 144bits with three multiplexing factors; 4, 8 and 16. The compiler allows designers to make trade-offs between various SRAM sizes in terms of number of words, word length and multiplex factor. It automatically generates datasheets, simulation (Verilog), layout (LEF) and timing/power (Liberty) models to enable standard EDA tool flows.
PowerMiser delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques have the added benefit of virtually eliminating performance compromises at low operating voltages. Retentive sleep modes, including light sleep for rapid wake-up as well as deep-sleep for maximal leakage current savings, are offered.
- Up to 60% dynamic power savings
- Up to 25% static power savings
- Low voltage operation down to 0.7V
- Avialable now
- Silicon proven in 28FDSOI & 40ULP