Ultra low power C-programmable DSP core

Features

• Ultra low power consumption
• 25 µW/MHz @ 0.9 V (65 nm CMOS)
• 45 µW/MHz @ 1.2 V (65 nm CMOS)
• 34 µW/MHz @ 0.9 V (90 nm CMOS)
• 60 µW/MHz @ 1.2 V (90 nm CMOS)
• 45 µW/MHz @ 0.9 V (130 nm CMOS)
• 80 µW/MHz @ 1.2 V (130 nm CMOS)
• 60 µW/MHz @ 0.9 V (180 nm CMOS)
• 240 µW/MHz @ 1.8 V in (180 nm CMOS)
• Highly optimizing C-compiler software toolkit
• Minimal core size (43k gates), excluding debug interface (6k gates)
• Small memory footprint
• Performance (Worst Case Commercial Conditions, standard VT)
• 160 MHz @ 1.8 V 180 nm CMOS
• 200 MHz @ 1.2 V 130 nm CMOS
• 245 MHz @ 1.2 V 90 nm CMOS
• 300 MHz @ 1.2 V 65 nm CMOS (>2300 MOPS peak)
• Extensive software library for audio decoding and advanced sound enhancement algorithms

Deliverables

• The CoolFlux DSP is available on FPGA board for testing and analyzing. Or you can evaluate the CoolFlux using the software toolkit.

Block Diagram of the Ultra low power C-programmable DSP core

• see the entire Ultra low power C-programmable DSP core datasheet
• get in contact with Ultra low power C-programmable DSP core Supplier