Ultra low power C-programmable DSP core
NXP distributes the CoolFlux DSP core through its corporate Innovation & Technology (I&T) division with license support of NXP's Intellectual Property & Licensing Department (IP&L).
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Block Diagram of the Ultra low power C-programmable DSP core

synthesizable IP
- Complete Neural Processor for Edge AI
- pico 2D Graphics Processor for Wearables/IoT
- I3C Slave
- PCIe 5.0 Controller IP supporting Root Complex, End Point, Switch Port compliant with PCIe 5.0/4.0/3.0/2.0/1.0 and fully synthesizable
- TFT/LCD/MIPI Display Controller and Composition Engine
- Input 12MHz, output 900 MHz/1200MHz, 600 MHz/800 MHz, 360 MHz/480MHz, 300 MHz/400MHz, frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process