Innopower provides the synchronous Via1 Programmable ROM (Via-ROM): The SP-type compiler, for various processes. This ROM can be incorporated with the Innopower standard cell library. Different combinations of words, bits, and aspect ratios can be used to generate the most desirable configurations.
Given the desired size and timing constraints, the Via1 Programmable ROM compiler is capable of providing the suitable synchronous ROM layout instances within minutes. It automatically generates the data sheets, Verilog / VHDL behavioral simulation models, P & R (place-and -route) models, and test patterns for use in the ASIC designs. The duty cycle length can be neglected as long as the setup/hold times and the minimum high/low pulse widths are satisfied. This provides a more flexible clock falling edge during each operation. Only one mask of Via1 layer is needed to be replaced.
- Supports synchronous read operations
- Via-1 layer programmable codes
- Supports Fully customized layout density
- Supports automatic power-down mechanism to eliminate DC current
- Clocked address inputs and CS to ROM at the CK rising edge
- Includes Verilog/VHDL timing/simulation model generators
- Includes SPICE netlist generator
- Includes GDSII layout database
- Memaker preview UI
- Supports BIST code supported for the best aspect ratio