Innopower provides the synchronous high-density Dual-Port-SRAM (DP-SRAM): The SJ-type compiler, for various processes. DP-SRAM can be incorporated with the Innopower standard cell library. Different combinations of words, bits, and aspect ratios can be used to generate the most desirable configurations. The DP-SRAM can support to read and to write the same address in one cycle. In certain process, the DP-SRAM compiler provides the option of row-redundancy. Moreover, certain process will provide the BIST interface option for customers.
Given the desired size and timing constraints, the Dual-Port-SRAM compiler is capable of providing the suitable synchronous RAM layout instances within minutes. It automatically generates the data sheets, Verilog/VHDL behavioral simulation models, P & R (place-and-rout) models, and test patterns to be used in the ASIC designs. The length of the duty cycle can be neglected as long as the setup/hold times and the minimum widths of high/low pulse are both satisfied. This allows a more flexible clock falling edge during each operation. Both word write and byte write operations are supported.