Implements a UART (Universal Asynchronous Receiver/Transmitter) core. It translates data between parallel and serial interfaces. Adds and removes start, stop and optionally parity bits. It can be used to communicate with other external devices using a serial cable and RS232 protocol. This core is fully compatible with industry standard National Semiconductors 16550D device. On power up it starts in 16450 mode. The UART core uses an AHB slave interface.
The UART core is rigorously verified, silicon-proven and available in RTL source or as a targeted FPGA netlist.
- AHB Interface
- After reset registers are in 16450 mode
- In FIFO mode transmitter and receiver data are buffered to reduce number of interrupts introduced to the CPU
- No synchronization is needed be-tween the UART core and the CPU because of transmit hold and receive hold registers respectively
- MODEM control functions
- Runtime configurable number of data bits
- Runtime configurable number of stop bits
- Odd, even, or no parity
- Internal diagnostic (loopback, er-ror simulation)
- Line break and detection
- Priority interrupt system control
- Compile time configurable memory access mode (byte or word)
- Synthesizable RTL or FPGA netlist
- Testbench & sample test cases
- Simulation & synthesis scripts
- The UART core can be used in a variety of serial communication applications including serial or modem computer interface, serial interface with modems and other devices.
Block Diagram of the Universal Asynchronous Receiver-Transmitter (16550D) IP Core