USB-C 3.2 SuperSpeed/SuperSpeedPlus PHY IP in TSMC N6
The DesignWare USB 3.2 Controller and PHY IP allow designers to maximize power efficiency for extended battery life. The DesignWare USB 3.2 IP enables the fastest USB data transfer speeds while lowering overall power consumption.
As the leading supplier of USB IP, Synopsys provides designers with a highperformance, low-power, and area-efficient IP solution, for cost-effective integration into system-on-chip designs. Synopsys’ expertise in developing and supporting USB enables us to build a low risk, high quality SuperSpeed USB IP solution.
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Video Demo of the USB-C 3.2 SuperSpeed/SuperSpeedPlus PHY IP in TSMC N6
It’s critical to understand the challenges around layout, power, specification details, the software stack and subsystem when it comes USB Type-C implementation. Join Morten Christiansen as he discusses what you should consider before implementing USB Type-C in your SoC design. Learn more about how Synopsys DesignWare USB IP can help bring your products to market at https://www.synopsys.com/usb.
USB PHY IP
- USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm)
- USB 3.1 PHY (10G/5G) in TSMC (16nm, 12nm, 7nm, 5nm)
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
- USB 3.1 PHY (10G/5G) in Samsung (14nm, 10nm, 11nm, 8nm, 5nm)
- USB 3.0 PHY Device/Host/OTG/Hub