SS V9012P is a USB 1.10 device core that can be readily interfaced with any industry standard microcontroller on one side and with any standard USB transceiver on the other side. The core implements all functionality required at physical (digital) layer and transaction layer of USB specification. The core reduces the load of the microcontroller. Automatic data retry is supported in the core and is not passed on to the higher level software layers.
The major blocks are the Serial Interface Engine (SIE), Function Interface Unit (FIU), EP Logic and Processor Interface Unit (PIU). SIE block handles NRZI decoding/encoding, CRC generation/ checking and bit de-stuffing/stuffing serial to parallel/ parallel to serial conversion and DPLL logic. EP Logic
handles routing of data to/ from the FIFO of the active endpoint. It selects the active endpoint, moves FIFO read/ write pointer to the appropriate location.
- Compliant with USB Specifications Revision 1.10
- Supports full speed (12 Mbps) operation
- Interfaces with most of the microcontrollers and microprocessors
- Megacell requests to CPU are interrupt driven to minimize the polling time requirements
- Configurability to select Endpoint sizes as allowed in USB Specification
- Configurability to select single or double buffer for any endpoint
- SoC Integration
- Fully synthesizable Verilog RTL source code
- Synthesis & STA constraints
- Synthesis Scripts
- STA scripts