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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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VESA DSC Decoder
The DesignWare® VESA Display Stream Compression (DSC) Decoder IP provides a video compression solution for up to 10K ultra-high-definition displays over HDMI 2.1, MIPI DSI, and VESA DisplayPort links. The IP enables designers to incorporate visually lossless data compression between the SoC and display to maximize video bandwidth and optimize power, and area for mobile, automotive, and AR/VR applications. Synopsys’ DesignWare VESA DSC IP, consisting of encoder and decoder, is compliant with the latest VESA DSC 1.2a and 1.1 specifications.
The IP interoperates with Synopsys’ DesignWare HDMI, MIPI DSI, and DisplayPort IP solutions to minimize integration risk and accelerate time-tomarket. The configurable IP transmits compressed data, distributed across up to 16 parallel slices in real time, to meet the performance and area requirements of target applications.
The DesignWare VESA DSC Decoder IP has been verified against the VESA DSC C-model and 100% coverage tested in an UVM-based verification environment, which is delivered with the IP.
The IP interoperates with Synopsys’ DesignWare HDMI, MIPI DSI, and DisplayPort IP solutions to minimize integration risk and accelerate time-tomarket. The configurable IP transmits compressed data, distributed across up to 16 parallel slices in real time, to meet the performance and area requirements of target applications.
The DesignWare VESA DSC Decoder IP has been verified against the VESA DSC C-model and 100% coverage tested in an UVM-based verification environment, which is delivered with the IP.
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