The DesignWare® VESA Display Stream Compression (DSC) Decoder IP provides a video compression solution for up to 10K ultra-high-definition displays over HDMI 2.1, MIPI DSI, and VESA DisplayPort links. The IP enables designers to incorporate visually lossless data compression between the SoC and display to maximize video bandwidth and optimize power, and area for mobile, automotive, and AR/VR applications. Synopsys’ DesignWare VESA DSC IP, consisting of encoder and decoder, is compliant with the latest VESA DSC 1.2a and 1.1 specifications.
The IP interoperates with Synopsys’ DesignWare HDMI, MIPI DSI, and DisplayPort IP solutions to minimize integration risk and accelerate time-tomarket. The configurable IP transmits compressed data, distributed across up to 16 parallel slices in real time, to meet the performance and area requirements of target applications.
The DesignWare VESA DSC Decoder IP has been verified against the VESA DSC C-model and 100% coverage tested in an UVM-based verification environment, which is delivered with the IP.
- The DesignWare VESA DSC Decoder IP supports a wide range of system designs with various configuration options.
- Interfaces – Device controller interface supports 48-bit, 64-bit, 96-bit,128-bit, 192-bit and 256-bit interface widths – Pixel interface supports 1, 2 or 4 pixels output per clock with line and slice markers Memory type support – Line buffer and rate buffer memories are based on single port RAM (1RW type) memory, offering static power and area savings versus two port RAM (1RW type) memory-based buffers
- Transport layer protocol support – HDMI 2.1 – VESA DisplayPort – MIPI-DSI/DSI-2
- Configurable features for gate count trade off – Block prediction – Number of slices per Line – Line buffer color depth – Color bit precision – Rate buffer size – Picture Parameter Set (PPS) /Capability Parameter Set (CPS) as registers or as I/Os
- Programmable features (for dynamic/run time enable/disable) – All PPS fields – Number of active slices per line – Drop/retain padded pixels at slice boundaries
- Clocking options – Single and separate clock options between device controller and decoder datapath Error reporting – Errors detected in PPS (PPS programmed not applicable in the target configuration) – Errors detected in decoder datapath
- Compliant with the VESA DSC 1.2a and 1.1 specifications
- Supports all DSC video formats: RGB, YCbCr, native 4:2:2/4:2:0, simple 4:2:2
- Supports latest interface standards: HDMI 2.1, MIPI DSI, DisplayPort
- Configurable IP delivers low-power and small area – Multiple slice decoding: 1, 2, 4, 8, 12, 16 – Precision: 8, 10, 12, 14, 16 bits – Selection of coding schemes (MMAP, BP, MPP, ICH)
- Single port RAM based buffers
- Picture Parameter Set (PPS)
- Highly programmable with APB-3 based register interface
- Error reporting for robust auto-recovery
- System Verilog RTL source/encrypted code
- ASIC and FPGA synthesis, ATPG, DFT, scripts
- VCS, Design Compiler, Spyglass, and Formality scripts
- Spyglass lint, CDC checker rules
- UVM Test bench with sanity tests
- Comprehensive data book, integration guides, installation guide and release notes
- AR/VR headsets
- Automotive display panels
- UHD television and home entertainment systems
- Professional audio video equipment
- Set-top boxes and game consoles
- HDMI 2.1 consumer electronics
- DisplayPort desktops/laptops