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WiMax Compliant Reed Solomon Decoder
The aim of Channel Coding is to insert redundancy in the transmitted information bit-stream. The redundant information is used by the Decoder module to correct the errors incurred by the channel. Block coding is based on finite field arithmetic and abstract algebra where Encoder and Decoder work on a block of bits at one time.
Reed-Solomon code is a linear systematic block code based on finite field theory.Reed-Solomon Encoder takes a block of digital data and adds extra "redundant" bits.Errors occur during transmission or storage for a number of reasons (for example noise or interference, scratches on a CD, etc). The Reed-Solomon decoder processes each block and attempts to correct errors and recovers the original data. The number and type of errors that can be corrected depends on the characteristics of the Reed-Solomon code.
Reed-Solomon code is a linear systematic block code based on finite field theory.Reed-Solomon Encoder takes a block of digital data and adds extra "redundant" bits.Errors occur during transmission or storage for a number of reasons (for example noise or interference, scratches on a CD, etc). The Reed-Solomon decoder processes each block and attempts to correct errors and recovers the original data. The number and type of errors that can be corrected depends on the characteristics of the Reed-Solomon code.
Features
- WiMAX (802.16-2004) compliant Reed Solomon Decoder
- · High Speed, High Throughput, Continuous mode decoding
- · Fully pipelined architecture between Decoder main blocks
- · Supports error only decoding
- · Key Equation solving using Berlekamp-Massey (BM) algorithm for efficient implementation
- · Option of using either low latency more area (Merged) BM architecture
- or high latency low area BM architecture (Re-use)
- · Use of special GF multiplier, which could be easily pipelined
- · Supports value of N equal to 255. Programmable codeword length (N)
- could be added
- · Corrects up to eight bit wide symbol errors. Programmable error correction capability (T) could be added
- · Code rate could be dynamically varied
- · Low Decoder latency and High throughput
- · Fully synchronous design with 8-bit input and output data busses
- · Un-correctable error handling support
- · Zero Error detection support in Syndromer block
- · Technology independent
Benefits
- The area for an RS Decoder depends on the architecture selected and the correction capability of the decoder. Optimizations could be done depending on the requirement. Minddecoders, due to its vast knowledge in Forward Error Correction domain could help in achieving High Speed, Low Area, Low latency implementations by selection of proper RS architectures
Deliverables
- . Design document describing the complete architecture level details
- · Complete Verification plan document
- · Well commented out high quality Synthesizable Verilog HDL source code
- · Complete verification environment with automated test bench
- · Complete suite of test vectors for verification
- · Source code in VHDL could also be provided on request
- · Simulation script, vectors and expected results
- · The core is available in FPGA (Netlist) forms, and includes everything
- required for successful implementation.
- · Expert Technical Support and Maintenance Update
View WiMax Compliant Reed Solomon Decoder full description to...
- see the entire WiMax Compliant Reed Solomon Decoder datasheet
- get in contact with WiMax Compliant Reed Solomon Decoder Supplier