Perceptual Mapping for Newly Developed 3rd Party IP
By Sanjeev Sharma (Terminus Circuits)
In recent time, 3rd party silicon IPs have proved to be cost-effective and catalyst for accelerated product development. Most of the program managers rely on well proven IPs with history of qualified customers and production data. The usual evaluation process is entirely skewed to a matured IP rather a newly developed IP.
The newly developed 3rd party IP comes with several risk factors, but it may also offer benefits like better performance, lower silicon area and better ROI proposition. A well-judged methodology to evaluate a 3rd party silicon IP may benefit from Time to Market perspective and it can reduce substantially reduce the NRE cost. Being an early adopter of this technology also helps the customer to work with 3rd party vendor for optimizing the IP as per their product requirement and hence avoiding the additional NRE towards customization.
Many customers have a detailed procedure for comparing and selecting 3rd Party IPs. Often this process run into time bound process and decisions are taken based on the “Performance” at the additional cost or “Low risk” at pricy point. Sometime customers just drop an idea of procuring the 3rd party IP due to non-availability of a pure rational method of selection criteria of 3rd Party IP.
This paper emphasizes the challenge and opportunities in the evaluation of new IPs being developed by 3rd Party vendor. Author suggests Perceptual Mapping technic for deciding the vendor offerings and project need. Also suggest some of the risk mitigations for a successful integration of the 3rd Party IP into the ASIC/SOC product.
This paper also recommend a practical engagement model from both engineering and business perspective for improvising the quality of IP deliverable and reducing the overall NRE cost of the IP development.
At the end, the paper discusses the adoption of complex IP, with the help of a business case in which the end customer takes a judicious decision and mitigates the risk at every level; hence successfully integrate a complex technology in his ASIC product. This case will also highlight the avenues for leveraging the development to reduce the NRE development cost and develop complex IP in most optimum way.