MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
New Silicon IP
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LPDDR4x Secondary/Slave (memory side!) PHY
- JEDEC standard LPDDR4X @ 4267 Mb per second per pin.
- Flexible channel architecture
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PLL_5nm
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PLL_40nm
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