AMBA-Xactor is proven VIP enabling SoC and IP developers to perform comprehensive functional verification of their IP and SOCs incorporating full range of AMBA bus protocols (AXI4 - Full, Lite, Stream, AXI3, AHB, APB) master, slave, and interconnects functionalities and ensure compliance to the AMBA standards.
VIP models are implemented in 100% native SystemVerilog UVM.
- Master, Slave, and Interconnect BFMs including passive interconnect monitor.
- Transaction class supports SV constraint sets for interleaving, out of order, early write data phase, inter-transaction and inter-beat delays, size/length, addressing
- ACE interconnect monitor verifies cache state transitions ACE supports N-way and fully associative cache
- Inject errors at all layers using callbacks and control slave completion response
- SV constraint set for transaction classes generates rich set of normal and error requests and responses
- Multi-level protocol trackers (Cache state, Channel) makes debugging faster
- Functional coverage tracks commands, addresses, and attributes
- Interfaces to ARM protocol checkers to isolate DUT bugs faster
- Comprehensive directed and constrained random examples of all transfer types
- Master, Slave, Interconnect BFMs
- Example testsuite
- User Guide