AMBA 3/4 AXI Verification IP provides an smart way to verify the AMBA 3/4 AXI component of a SOC or a ASIC. The SmartDV's AMBA 3/4 AXI Verification IP is fully compliant with standard AMBA 3/4 AXI Specification and provides the following features.
AMBA 3/4 AXI VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA and non-standard verification env
- Compliant with the latest ARM AMBA 3 AXI specification.
- Supports AXI Master, AXI Slave, AXI Monitor and AXI Checker.
- Supports all ARM AMBA 3 AXI data and address widths.
- Supports all protocol burst types, burst lengths and response types.
- Supports constrained randomization of protocol attributes.
- Ability to issue multiple outstanding transactions.
- Out of order transaction completion support.
- Write data and read data interleaving support.
- Support for burst-based transactions with only start address issued.
- Unaligned data transfers using byte strobes.
- Separate address/control and data phases. Separate read and write data channels.
- Atomic access support
- Locked response
- Protected accesses
- Configurable write and read interleave depth
- Slave supports fine grain control of response per address or per transaction.
- Configurable wait states on different channels.
- Supports FIFO memory.
- Rich set of configuration parameters to control AXI functionality.
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Built in coverage analysis.
- Callbacks in master, slave and monitor for various events.
- Status counters for various events on bus.
- AXI Verification IP comes with complete testsuite to test every feature of ARM AMBA 3 AXI specification.
- Faster testbench development and more complete verification of AMBA 3/4 AXI designs.
- Easy to use command interface simplifies testbench control and configuration of master and slave.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete SystemVerilog source code of AMBA 3/4 AXI Arbiter, AXI Master, AXI Slave, AXI Monitor and AXI Checker.
- Complete regression suite containing all the AMBA 3 AXI testcases.
- Examples's showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.