The AMBA 5 CHI Verification IP is ready-made for your environment, providing consistent results whether you are using Cadence Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Cadence Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.
- Supports link, network and protocol layer communication, including flow control mechanisms, across all RnX-to-HnX and HnX-to-SnX links
- Models the cache in RnF-to-HnF link
- Each link can take the part of either node as an active agent generating requests/snoops and responding according to the requests sent its way, or as a passive agent monitoring protocol correctness and collecting functional coverage