AMBA AHB VIP can be configured as Master, Slave and AHB bus and allows Module & System level verification. AMBA AHB VIP is a readymade highly configurable SystemVerilog Verification Component suitable for verification of AMBA AHB master and slave DUT. The AHB SV VIP provides all necessary building blocks to easily test master/slave DUT with the AHB protocol. The Verification Component can be easily configured and integrated with the verification environment.
- Generate Busy, Idle or burst transfers on the AHB bus
- Gives arbitration at three level of arbitration priority level
- Generates different kind of response like SPLIT, RETRY, ERROR and OKAY
- Collects coverage information
- Checks for AMBA AHB protocol through interface level assertion
- Support for all kind of burst transfers like SINGLE/INCR/WRAP
- Support for different size (HSIZE) of transfer
- Support for multiple bus-widths (32/64 bits)
- eInfochips provides customer's regular product updates and consultation with experts. Our Verification experts are available round the clock to meet customer requirements related to integrating verification components into test environment and other support related issues.
- Completely verified AHB Verification Component encrypted code
- Documentation - User's Guide, Release Notes
- Sample Test cases
Block Diagram of the AMBA AHB Verification IP Verification IP